It is common to induce horizontal tensile stress in n-channel metal oxide semiconductor (NMOS) transistors in integrated circuits (ICs) in order to improve on-state drive current and off-state leakage current. Processes such as stress memorization techniques and inclusion of tensile stress pre-metal dielectric liners frequently result in tensile stress levels above 1000 MPa. NMOS transistors are susceptible to stress induced defects which cause excess leakage current. Stress induced defects are sensitive to variations in active area and gate configurations. Detection and isolation of stress induced defects is problematic, because stress induced defects have little or no visibly observable signature and typically require analysis by transmission electron microscopy (TEM) for confirmation.